In a NAND gate when the
input threshold voltage crosses in the positive direction the output
will cross the threshold voltage in the negative direction without
any delay in a ideal circuit. But in practical circuits the output
will lag the input by some time. See the graph below
In the graph we can see
that there is a time delay of t1 between the input and output when
the when input crosses the positive threshold and the output crossing
the negative threshold. Also we can see that there is a time delay of
t2 between the negative transition of input and positive transition
of output.
The transition of logic
level from 0 to 1 is called dynamic 1 and the downward transition of 1 to 0 is
called dynamic 0.
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