Working of a basic sequential circuit

In this article we will explain how a basic sequential circuit works and how its output is dependent on the previous inputs.Consider the figure below

In the figure we have two NOR gate connected such that the output of one NOR gate becomes one of the input of the other gate. The two inputs R and S are the primary inputs and can be changed when we need. But this circuit shown above is not a practical one because it has no delay. In real world every nor gate will be associated with some delay . The diagram along with delay is shown in figure below.

Here the two gates have a delay of “d”. Their outputs x and y becomes X and Y after a delay of d. By the examination of equivalent circuit we found that the output x and y follow changes in input R,S,X and Y instantaneously. From this observation we write the combinatorial relationships as

X and Y are nothing but x and y delayed for some time. So we can write

X(t) =x(t-d) Y(t) =y(t-d)

We can represent x and y (eq.1) in K-maps as shown below.

For simplicity we combine the two k-map into one as shown below.

With K-map we cannot find the sequence of events ,but we can find out the state of the circuit at a particular time using K-Map. Ie we can determine what happens after a time delay d just by saying X becomes x and Y becomes y after a time delay d.

The circuit is stable when x= X and y=Y. In all other cases the circuit is unstable and further changes must be take place to make the circuit stable . In a K- map stable states can be identified by comparing the XY values of each row and the entries of xy in the same row.

Sequence of events or cycles by which the sequential switching circuit come to a stable state.

Consider that the circuit is in a unstable condition where RS= 10 and XY =11 (4^th column 3^rd row). We can see that the value of xy at this position 00 and is not equal to the value of XY. But XY assumes the value of xy(as it is given as feed back) after some time and now becomes 00. So our point of attention moves to 4^th column 1^st row . Here also its unstable since xy =01 and is not equal to XY. So after some time XY becomes 01 and our point of attention moves to 2^nd row 1^st column. Here xy = 01 which is equal to XY . This is a stable situation.

Proving that sequential switching circuit exhibit memory.

When the primary input RS has value 00 it can assume two stable states where XY=01(A) or 10 (B). But what was RS before it became 00. It could have been 01 or 10 from which they changed one digit to become 00.

Suppose that RS was equal to 01 and the circuit was in stable state C. We now make S=0 making RS=00 making us move to the first column to reach the stable state B.

Suppose RS was equal to to 10 and the circuit was in stable state E. We now make R=0 making RS=00 making us move to the first column to reach the stable state A.

Thus we clearly prove that sequential switching circuit ie it outputs depend on previous inputs.

Oscillatory and Bistable output

Consider three inverters connected like in the figure. The output is fed back to the input. This circuit has no primary inputs. To understand the working of the loop consider that at t=0 there is a noise induced dynamic '1'. This will propagate through the gates and give an output of dynamic 0 at t= 2t1 + t2 . T1 and t2 are propagation delays of the gates. This will go on endlessly. Thus the output of any gate will be oscillatory. An oscillatory output is also called unstable.

If we have even number of gates we can be see that the output can only be 0 or 1

Sequential switching circuit

In a NAND gate when the input threshold voltage crosses in the positive direction the output will cross the threshold voltage in the negative direction without any delay in a ideal circuit. But in practical circuits the output will lag the input by some time. See the graph below

In the graph we can see that there is a time delay of t1 between the input and output when the when input crosses the positive threshold and the output crossing the negative threshold. Also we can see that there is a time delay of t2 between the negative transition of input and positive transition of output.

The transition of logic level from 0 to 1 is called dynamic 1 and the downward transition of 1 to 0 is called dynamic 0.

Basic structure of a transistor.

A transistor has three regions

The emitter : This is heavily doped. Its function is to emit electrons or holes into the transistor.

The base: It is in between the collector and emitter. It is lightly doped. It passes most of the charge carriers from the emitter to the collector.

The collector: It collects the charge carriers from the emitter. It doping is less than emitter but higher than that of base.

2's complement arithmetic

Addition of two positive number: The addition of positive number follows the same rules that of the binary addition.

The magnitude of the sum should be in range(ie it should not go out of range of the system). If the sum goes out of range the sign bit will become 1.

Eg

+8   0,1000

+10 0,1010

---------

1,0010 (This answer is incorrect because in here we consider a 4bit operands)

2's complement subtraction: It is the addition of minuend to the 2's complement of the subtrahend. The sign bits of the two numbers are considered as a part of the number and is used in the addition.

Eg +5 0,0101

      -3 1,1101 (2's complement of 3)

         ---------

   +2 10,0010          (the one is ignored) 

The over flow produced in the addition is ignored. The bit in the sign bits position will be the correct sign bit after addition. If the result is negative it will be in 2's complement form.

Eg -5 1,1011

    +3 0,0011

       --------

    -2 1,1110

Addition of two negative numbers in 2's complement form: Here also the over flow bit is discarded. The sign bit is correct if the result is in the allowed range(for 4 bit operand the range is <=15). The sign bit will become 1 indicating error if the answer goes out of range.

Eg -5 1,1011

     -3 1,1101

        ---------

    -8 11,1000

Eg -8 1,1000

     -9 1,0111

      ----------

       10,1111 (not correct as the result goes out of range)

Ones complement arithmetic

consider the arithmetic x-y and x+y. For computing these two equations in the normal way we need two different circuits because they do different two operations. The use of ones complement comes here as x-y can be also represented as x+ 1's complement of y. This eliminates the use of two different circuits for addition and subtraction.

In our examples below we use 4 bit numbers and assumes that the um should be less than or equal to 15. If it exceeds 15 we will get an incorrect answer. 

+3=	0,	0	0	1	1
+7=	0,	0	1	1	1
+10	0,	1	0	1	0

+8=	0,	1	0	0	0
+9=	0,	1	0	0	1
	1,	0	0	0	1

Not correct as the sum exceeds 15

Addition rules

1. If an over flow is produced beyond the sign bit while adding two signed numbers, then the over flow bit is removed and added to the result. The examples below explains it.
   
   
   
   
   
   2. If a positive number is added to a negative number and does not result in a over flow , then the result is negative and is in ones complement form. An example is given below.
   
   
   -5 1, 1 0 1 0
   +3 0, 0 0 1 1
   -2 1, 1 1 0 1   
   
   
   3. If two negative numbers are added there will be a over flow. This over flow bit is added to the result. The sign will be that of the final answer. The magnitude of the sum should be less than 15 in this case as we use only 4 bit operands. Some examples are shown below.  
   
   
   
   
   
   
   
   
   
   
   
   

Compliment representation of numbers

In sign magnitude system the sign of a binary number is denoted by a extra bit in-front of the number.

For example +5 is denoted by 0,101.

0 : show that the number is positive

1: show that the number is negative

Ones compliment

In ones compliment system the representation of positive number is the same as that of sign magnitude system. But the representation of negative number is different.

For example -5 is represented in ones compliment as 1,010. This is obtained by replacing all the 1s by 0 and zero by 1 in the binary representation of +5 which is 0,101.

The process of replacing a 0 by 1 and 1 by 0 is called bits complimenting.

In general a n bit number x's (with out sign bit) ones compliment is given by (2^n-1-x).

Twos compliment

The twos compliment is obtained by adding 1 to the ones compliment of a number.

Example:

+5=0,101

-5=1,010 (1s compliment)

now twos compliment of -5 is 1,010 + 0001 = 1,011

In general for an n bit number twos compliment is given by 1,(2^n-x). Another method to to find the twos compliment of a binary number is to scan the number from left to right and compliment all the bits appearing after the first one. An example I given below.

0,1110 → 1,0010